数字系统设计入门教程-集成方法 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

数字系统设计入门教程-集成方法 英文版PDF格式电子书版下载

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Chapter 1 Concepts in Digital Systems1

1．1 What Is a Digital System?1

1．2 Views of a Digital System2

1．2．1 Hierarchies2

1．2．2 The Personal Computer3

1．3 Introduction to Binary Numbers4

1．4 Data Representations6

1．5 Binary and Decimal Numbers8

1．5．1 Binary-to-Decimal Conversion8

1．5．2 Decimal-to-Binary Conversion10

1．5．3 Fractions12

1．5．4 Hexadecimal Numbers14

1．6 Cells and Hierarchy15

1．7 System Primitives19

1．8 Metrics22

1．9 Hierarchical Plan for the Book23

1．10 Problems26

Chapter 2 Boolean Algebra and Logic Gartes29

2．1 Data Representation and Processing29

2．2 Basic Logic Operations31

2．2．1 The NOT Operation31

2．2．2 The OR Gate32

2．2．3 The AND Gate33

2．3 Basic Identities35

2．3．1 NOT Identity35

2．3．2 OR Identities35

2．3．3 AND Identities36

2．4 Algebraic Laws37

2．4．1 Commutative Laws37

2．4．2 Associative Laws37

2．4．3 Distributive Laws38

2．5 NOR and NAND Gates39

2．5．1 DeMorgan Theorems41

2．6 Useful Boolean Identities43

2．7Algebraic Reductions44

2．8 Complete Logic Sets47

2．8．1 NAND-Based Logic48

2．8．2 NOR-Based Logic48

2．9 IEEE Logic Gate Symbols49

2．10 Problems50

Chapter 3 Combinational Logic Design57

3．1 Specifying the Problem57

3．2 Canonical Logic Forms59

3．2．1 Sum-of -Products（SOP） Form59

3．2．2 Product-of-Sums（POS）Form60

3．3 Extracting Canonical Forms61

3．3．1 Minterms and Maxterms63

3．3．2 Properties of SOP and POS Forms65

3．4The Exclusive-OR and Equivalence Operations66

3．5 Logic Arrays68

3．5．1 AND and OR Arrays69

3．5．2 SOP and POS Arrays71

3．5．3 Application of Logic Arrays75

3．6 BCD and 7-Segment Displays76

3．7 Karnaugh Maps80

3．7．1 2-Variable Karnaugh Maps81

3．8 3-Variable Karnaugh Maps84

3．8．1“Don t Care”Conditions88

3．8．2 Alternative 3-Variable Map Layout89

3．9 4-Variable Karnaugh Maps89

3．10 The Role of the Logic Designer93

3．11 Problems94

Chapter 4 Digital Hardware101

4．1 Voltages as Logic Variables101

4．1．1 Logic Levels103

4．2 Digital Integrated Circuits104

4．2．1 Integration Levels108

4．3 Logic Delay Times109

4．3．1 Output Switching Times110

4．3．2 The Propagation Delay111

4．3．3 Fan-Out and Fan-In112

4．3．4 Extension to Other Logic Gates115

4．3．5 Logic Cascades116

4．4 Basic Electric Circuits119

4．4．1 Resistance120

4．4．2 Capacitance122

4．4．3 The RC Circuit123

4．4．4 Application to Digital Circuits128

4．5 Transmission Lines128

4．5．1 Crosstalk130

4．5．2 Electromagnetic Interference131

4．6 Logic Families132

4．6．2 TTL Integrated Circuits133

4．6．1 CMOS133

4．6．3 Emitter-Coupled Logic（ECL）134

4．7 The Hardware Designer135

4．8 Problems135

Chapter 5 First Concepts in VHDL143

5．1 Introduction143

5．1．1 Basic Concepts144

5．1．2 Using a Hardware Description Language145

5．2 Defining Modules in VHDL145

5．2．1 Concurrent Operations152

5．2．2 Identifiers155

5．2．3 Propagation Delay156

5．3 Structural Modeling158

5．4 Conditional Models163

5．5 Binary Words167

5．6 Libraries169

5．7 Learning VHDL171

5．8 Problems172

Chapter 6 CMOS Logic Circuits177

6．1 CMOS Electronics177

6．2 Electronic Logic Gates178

6．3 MOSFETs179

6．4The NOT Function in CMOS183

6．4．1 Complementary Pairs185

6．4．2 The CMOS Inverter186

6．5 Logic Formation Using MOSFETs187

6．5．1 The NOR Gate190

6．5．2 The NAND Gate192

6．5．3 The CMOS-Logic Connection193

6．6 Complex Logic Gates in CMOS195

6．6．1 3-Input Logic Gates196

6．6．2 A General 4-Input Gate199

6．6．3 Logic Cascades201

6．7 MOSFET Logic Formalism202

6．7．1 FET Logic Descriptions203

6．7．2 Voltage Transmission Characteristics204

6．7．3 The Complementary Principle206

6．7．4 Current Switching208

6．7．5 Fiber-Optic Transmission Networks210

6．8 Problems212

Chapter 7 Silicon Chips and VLSI219

7．1 What Is VISI Engineering?219

7．1．1 Inside a Computer Chip220

7．1．2 A Silicon Primer220

7．1．3 The pn Junction224

7．1．4 Silicon Devices225

7．2 Lithography and Patterning226

7．2．1 The Importance of Physical Layout229

7．3 MOSFETs230

7．3．1 MOSFET Switching232

7．3．2 pFETs237

7．3．3 MOSFET Design Rules240

7．3．4 The Incredible Shrinking Transistor241

7．4 Basic Circuit Layout244

7．4．1 The CMOS Inverter245

7．4．2 Electrical Modeling246

7．5 MOSFET Arrays and AOI Gates254

7．5．1 Wiring Strategies254

7．5．2 NAND and NOR Layout256

7．5．3 Complex Logic Gates257

7．5．4 General Observations258

7．6 Cells,Libraries,and Hierarchical Design259

7．6．1 Creation of a Cell Library260

7．6．2 Cell Placement262

7．6．3 System Hierarchies262

7．7 Floorplans and Interconnect Wiring264

7．7．1 Interconnects266

7．7．2 Wiring Delays268

7．8 Problems270

Chapter 8 Logic Components275

8．1 Concept of a Digital Component275

8．2 An Equality Detector276

8．3 BCD Validity Detector278

8．4 Line Decoders280

8．5 Multiplexors283

8．5．1 Multiplexors as Logic Elements286

8．5．2 VHDL Description288

8．6 Demultiplexors289

8．6．1 VHDL Description290

8．6．2 Multiplexed Transmission System291

8．7 Binary Adders292

8．7．1 The Full-Adder293

8．7．3 Adder Cricuits294

8．7．2 Half-Adders294

8．7．4 VHDL Descriptions296

8．7．5 Parallel Adders298

8．7．6 CMOS Adder Circuits300

8．8 Subtraction301

8．8．1 Subtractor Logic Circuits307

8．8．2 Negative Numbers308

8．9 Multiplication311

8．10 Transmission Gate Logic314

8．10．1 Transmission Gate Multiplexors315

8．10．2 TG XOR and XNOR Gates317

8．10．3 CMOS Transmission Gates318

8．11 Summary319

8．12 Problems320

Chapter 9 Memory Elements and Arrays327

9．1 General Properties327

9．2．1 The SR Latch328

9．2 Latches328

9．2．2 D Latch331

9．3 Clocks and Synchronization332

9．3．1 Clocked SR Latch333

9．3．2 The D Latch334

9．4 Master-Slave and Edge-Triggered Flip-Flops334

9．4．1 A Master-Slave D-Type Flip-Flop335

9．4．2 Other Types of Flip-Flops341

9．5 Registers343

9．5．1 Basic Storage Register343

9．5．2 Shift Registers344

9．6 Random-Access Memory（RAM）348

9．6．1 Static RAM Cell348

9．6．2 SRAM Array350

9．6．3 Dynamic RAM353

9．6．4 Parity and Error-Detection Codes354

9．8 CD ROM356

9．7 Read-Only Memory（ROM）356

9．9 CMOS Memories362

9．9．1 CMOS SRAMs362

9．9．2 Dynamic RAM363

9．9．3 ROMs366

9．10 Transmission-Gate Circuits367

9．10．1 Basic Latch367

9．10．2 TG Flip-Flop369

9．11 Problems370

Chapter 10 Sequential Logic Networks375

10．1 The Concept of a Sequential Network375

10．1．1 Sequential Network Requirements377

10．1．2 A General Sequential Network379

10．2 Analysis of Sequential Networks380

10．2．1 Single-State Variable Circuits381

10．2．2 Multi-State Variable Networks386

10．3 Sequential Network Design389

10．2．3 General Characteristics389

10．4 Binary Counters391

10．5 The Importance of State Machines397

10．6 Problems397

Chapter 11 Computer Basics403

11．1 An Overview of Computer Operations403

11．1．1 Major Components of a Computer404

11．1．2 What Can a Computer Do?405

11．1．3 The von Neumann Model405

11．1．4 Programming407

11．1．5 Computer Registers409

11．2 The Central Processor Unit:A First Look409

11．2．1 The Instruction Fetch Network410

11．2．2 Concept of the Datapath412

11．2．3 Datapath Operations413

11．3 Datapath Components415

11．3．1 The Register File416

11．3．2 The Arithmetic and Logic Unit418

11．3．3 The Local Memory423

11．4 Instructions and the Datapath423

11．5 The Control Uint431

11．6 CISC and RISC Architectures435

11．6．1 CISC and Microprogramming436

11．6．2 RISC Machines437

11．6．3 Modern Computers440

11．7 Floating-Point Operations440

11．7．1 Arithmetic Operations442

11．7．2 Application to Computers443

11．8 VLSI Aspects of Computer Design444

11．9 Problems446

Chapter 12 Advanced Computer Concepts451

12．1 Computing Speed451

12．2 Pipelining452

12．2．1 Data Hazards457

12．2．2 Resolving Hazards460

12．3Cache Memory461

12．3．1 VLSI Aspects of Cache Memory464

12．4 Superscalar Architectures468

12．5 Basic Concepts of Parallel Computing470

12．5．1 Classifications of Parallel Machines473

12．5．2 Examples of Parallel Computations475

12．5．3 General Architectures479

12．5．4 General Design Variables481

12．5．5 Interconnection Networks482

12．5．6 The Challenge of Parallel Computing484

12．5．7 Optical Interconnects484

12．6 Problems486

12．7 References489

Epilog491

Index493