数字集成电路与嵌入式内核系统可测试性设计2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

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1 Test and Design-for-Test Fundamentals1

1.1 Introduction to Test and DFT Fundamentals3

1.1.1 Puupose3

1.1.2 Introduction to Test,the Test Process,and Design-for-Test3

1.1.3 Concurrent Test Engineering4

1.2 The Reasons for Testing7

1.2.1 Why Test?Why Add Test Logic?7

1.2.2 Pro and Con Perceptions of DFT7

1.3.1 What Is Testing?10

1.3 The Definition of Testing10

1.3.2 Stimulus11

1.3.3 Response11

1.4 Test Measurement Criteria13

1.4.1 What Is Measured?13

1.4.2 Fault Metric Mathematics14

1.5 Fault Modeling16

1.5.1 Physical Defects16

1.5.2 Fault Modeling16

1.6.3 Combinational Exhaustive and Pseudo-Exhaustive Testing20

1.6.2 Structural Testing20

1.6.1 Functional Testing20

1.6 Types of Testing20

1.6.4 Full Exhaustive Testing21

1.6.5 Test Styles21

1.7 Manufacturing Test23

1.7.1 The Manufacturing Test Process23

1.7.2 Manufacturing Test Load Board23

1.7.3 Manufacturing Test Program23

1.8.3 ATE Cost Considerations25

1.8.2 ATE Limitations25

1.8.1 Automatic Test Equipment25

1.8 Using Automatic Test Equipment25

1.9 Test and Pin Timing27

1.9.1 Tester and Device Pin Timing27

1.9.2 Tester Edge Sets27

1.9.3 Tester Precision and Accuracy28

1.10 Manufacturing Test Program Components30

1.10.1 The Pieces and Parts of a Test Program30

1.10.2 Test Program Optimization32

1.11 Recommended Reading33

2 Automatic Test Pattern Generation Fundamentals35

2.1.2 Introduction to Automated Test Pattern Generation37

2.1.1 Purpose37

2.1 Introduction to Automatic Test Pattern Generation37

2.1.3 The Vector Generation Process Flow38

2.2 The Reasons for ATPG41

2.2.1 Why ATPG?41

2.2.2 Pro and Con Perceptions of ATPG41

2.3 The Automatic Test Pattern Generation Process44

2.3.1 Introduction to ATPG44

2.4 Introducing the Combinational Stuck-At Fault47

2.4.1 Combinational Stuck-At Faults47

2.4.2 Combinational Stuck-At Fault Detection47

2.5.2 Delay Fault Detection49

2.5 Introducing the Delay Fault49

2.5.1 Delay Faults49

2.6 Introducing the Current-Based Fault52

2.6.1 Current-Based Testing52

2.6.2 Cuffent-Based Testing Detection52

2.7 Testability and Fault Analysis Methods54

2.7.1 Why Conduct ATPG Analysis or Testability Analysis?54

2.7.2 What Types of Testability Analysis Are Available?54

2.7.3 Fault Effective Circuits54

2.7.4 Controllability-Observability Analysis55

2.7.5 Circuit Learning56

2.8.1 Causes and Effects of Fault Masking58

2.8.2 Fault Masking on Various Fault Models58

2.8 Fault Masking58

2.9 Stuck Fault Equivalence60

2.9.1 Fault Equivalence Optimization60

2.9.2 Fault Equivalence Side Effects60

2.10 Stuck-At ATPG62

2.10.1 Fault Selection62

2.10.2 Exercising the Fault63

2.10.3 Detect Path Sensitization63

2.11.1 Using ATPG with Transition Delay Faults65

2.11 Transition Delay Fault ATPG65

2.11.2 Transition Delay Is a Gross Delay Fault66

2.12 Path Delay Fault ATPG68

2.12.1 Path Delay ATPG68

2.12.2 Robust Fault Detection68

2.12.3 The Path Delay Design Description69

2.12.4 Path Enumeration69

2.13 Current-Based Fault ATPG71

2.13.1 Current-Based ATPG Algorithms71

2.14.1 Multiple Cycle Sequential Test Pattern Generation73

2.14 Combinational versus Sequential ATPG73

2.14.2 Multiple Time Frame Combinational ATPG74

2.14.3 Two-Time-Frame ATPG Limitations75

2.14.4 Cycle-Based ATPG Limitations75

2.15 Vector Simulation77

2.15.1 Fault Simulation77

2.15.2 Simulation for Manufacturing Test77

2.16 ATPG Vectors80

2.16.1 Vector Formats80

2.16.2 Vector Compaction and Compression80

2.17.1 The ATPG Tool NO Rules List83

2.17 ATPG-Based Design Rules83

2.17.2 Exceptions to the Rules84

2.18 Selecting an ATPG Tool87

2.18.1 The Measurables87

2.18.2 The ATPG Benchmark Process88

2.19 ATPG Fundamentals Summary91

2.19.1 Establishing an ATPG Methodology91

2.20 Recommended Reading92

3 Scan Architectures and Techniques93

3.1.2 The Testing Problem95

3.1.1 Purpose95

3.1 Introduction to Scan-Based Testing95

3.1.3 Scan Testing96

3.1.4 Scan Testing Misconceptions96

3.2 Functional Testing99

3.3 The Scan Effective Circuit101

3.4 The Mux-D Style Scan Flip-Flops103

3.4.1 The Multiplexed-D Flip-Flop Scan Cell103

3.4.2 Perceived Silicon Impact of the Mux-D Scan Flip-Flop103

3.4.3 Other Types of Scan Flip-Flops103

3.4.4 Mixing Scan Styles104

3.5 Preferred Mux-D Scan Flip-Flops106

3.5.1 Operation Priority of the Multiplexed-D Flip-Flop Scan Cell106

3.5.2 The Mux-D Flip-Flop Family106

3.6 The Scan Shift Register or Scan Chain108

3.6.1 The Scan Architecture for Test108

3.6.2 The Scan Shift Register(a.k.a The Scan Chain)108

3.7 Scan Cell Operations110

3.7.1 Scan Cell Transfer Functions110

3.8 Scan Test Sequencing112

3.9 Scan Test Timing115

3.10 Safe Scan Shifting118

3.11 Safe Scan Sampling:Contention-Free Vectors120

3.11.1 Contention-Free Vectors120

3.12 Partial Scan122

3.12.1 Scan Testing with Partial-Scan122

3.12.2 Sequential ATPG122

3.13 Multiple Scan Chains125

3.13.1 Advantages of Multiple Scan Chains125

3.13.2 Balanced Scan Chains125

3.14.2 The Shared Scan Input Interface128

3.14.1 Setting up a Borrowed Scan Interface128

3.14 The Borrowed Scan Interface128

3.14.3 The Shared Scan Output Interface129

3.15 Clocking,On-Chip Clock Sources,and Scan131

3.15.1 On-Chip Clock Sources and Scan Testing131

3.15.2 On-Chip Clocks and Being Scan Tested131

3.16 Scan-Based Design Rules134

3.16.1 Scan-Based DFT and Design Rules134

3.16.2 The Rules134

3.17.1 DC Scan Insertion139

3.17.2 Extras139

3.17 Stuck-At(DC)Scan Insertion139

3.17.3 DC Scan Insertion and Multiple Clock Domains140

3.18 Stuck-At Scan Diagnostics142

3.18.1 Implementing Stuck-At Scan Diagnostics142

3.18.2 Diagnostic Fault Simulation142

3.18.3 Functional Scan-Out143

3.19 At-Speed Scan(AC)Test Goals145

3.19.1 AC Test Goals145

3.19.2 Cost Drivers145

3.20.2 At-Speed Scan Sequence148

3.20.3 At-Speed Scan versus DC Scan148

3.20.1 Uses of At-Speed Scan Testing148

3.20 At-Speed Scan Testing148

3.21 The At-Speed Scan Architecture150

3.21.1 At-Speed Scan Interface150

3.21.2 At-Speed Safe Shifting Logic150

3.21.3 At-Speed Scan Sample Architecture150

3.22 The At-Speed Scan Interface152

3.22.1 At-Speed Scan Shift Interface152

3.22.2 At-Speed Scan Sample Interface152

3.23 Multiple Clock and Scan Domain Operation154

3.23.1 Multiple Timing Domains154

3.24.1 Multiple Clock Domains,Clock Skew,and Scan Insertion157

3.24 Scan Insertion and Clock Skew157

3.24.2 Multiple Time Domain Scan Insertion158

3.25 Scan Insertion for At-Speed Scan161

3.25.1 Scan Cell Substitution161

3.25.2 Scan Control Signal Insertion161

3.25.3 Scan Interface Insertion161

3.25.4 Other Considerations161

3.26.1 Critical Paths163

3.26.2 Critical Path Selection163

3.26 Critical Paths for At-Speed Scan163

3.26.3 Path Filtering164

3.26.4 False Path Content165

3.26.5 Real Critical Paths166

3.26.6 Critical Path Scan-Based Diagnostics166

3.27 Scan-Based Logic BIST168

3.27.1 Pseudo-Random Pattern Generation168

3.27.2 Signature Analysis168

3.27.3 Logic Built-In Self-Test168

3.27.4 LFSR Science(A Quick Tutorial)169

3.27.6 Aliasing170

3.27.5 X-Management170

3.28 Scan Test Fundamentals Summary173

3.29 Recommended Reading174

4 Memory Test Architectures and Techniques175

4.1 Introduction to Memory Testing177

4.1.1 Purpose177

4.1.2 Introduction to Memory Test177

4.2 Types of Memories180

4.2.1 Categorizing Memory Types180

4.3.1 Types of Memory Organization183

4.3 Memory Organization183

4.4 Memory Design Concerns186

4.4.1 Trade-Offs in Memory Design186

4.5 Memory Integration Concerns188

4.5.1 Key Issues in Memory Integration188

4.6 Embedded Memory Testing Methods190

4.6.1 Memory Test Methods and Options190

4.7 The Basic Memory Testing Model193

4.7.1 Memory Testing193

4.7.2 Memory Test Fault Model193

4.7.3 Memory Test Failure Modes193

4.8.1 Stuck-At Based Memory Bit-Cell Fault Models195

4.8.2 Stuck-At Fault Exercising and Detection195

4.8 The Stuck-At Bit-Cell Based Fault Models195

4.9 The Bridging Defect-Based Fault Models197

4.9.1 Bridging Defect-Based Memory Test Fault Models197

4.9.2 Linking Defect Memory Test Fault Models197

4.9.3 Bridging Fault Exercising and Detection197

4.10 The Decode Fault Model199

4.10.1 Memory Decode Fault Models199

4.10.2 Decode Fault Exercising and Detection199

4.11.2 DRAM Refresh Requirements201

4.11 The Data Retention Fault201

4.11.1 Memory Test Data Retention Fault Models201

4.12 Diagnostic Bit Mapping203

4.12.1 Memory Test Diagnostics:Bit Mapping203

4.13 Algorithmic Test Generation205

4.13.1 Introduction to Algorithmic Test Generation205

4.13.2 Automatic Test Generation205

4.13.3 BIST-Based Algorithmic Testing206

4.14.3 Input Observation208

4.14.2 Memory Interaction Methods208

4.14.4 Output Control208

4.14 Memory Interaction with Scan Testing208

4.14.1 Scan Test Considerations208

4.15 Scan Test Memory Modeling210

4.15.1 Modeling the Memory for ATPG Purposes210

4.15.2 Limitations210

4.16 Scan Test Memory Black-Boxing212

4.16.1 The Memory Black-Boxing Technique212

4.16.2 Limitations and Concerns212

4.17 Scan Test Memory Transparency214

4.17.1 The Memory Transparency Technique214

4.17.2 Limitations and Concerns214

4.18.2 Limitations and Concerns216

4.18 Scan Test Memory Model of The Fake Word216

4.18.1 The Fake Word Technique216

4.19 Memory Test Requirements for MBIST218

4.19.1 Memory Test Organization218

4.20 Memory Built-In Self-Test Requirements220

4.20.1 Overview of Memory BIST Requirements220

4.20.2 At-Speed Operation220

4.21 An Example Memory BIST222

4.21.1 A Memory Built-In Self-Test222

4.21.2 Optional Operations223

4.21.3 An Example Memory Built-In Self-Test223

4.22.1 Integrating Memory BIST225

4.22 MBIST Chip Integration Issues225

4.23 MBIST Integration Concerns227

4.23.1 MBIST Default Operation227

4.24 MBIST Power Concerns229

4.24.1 Banked Operation229

4.25 MBIST Design—Using LFSRs231

4.25.1 Pseudo-Random Pattern Generation for Memory Testing231

4.25.2 Signature Analysis and Memory Testing231

4.25.3 Signature Analysis and Diagnostics231

4.26.2 Output Assessment234

4.26.1 Shift-Based Memory Testing234

4.26 Shift-Based Memory BIST234

4.27 ROM BIST236

4.27.1 Purpose and Function of ROM BIST236

4.27.2 The ROM BIST Algorithm237

4.27.3 ROM MISR Selection237

4.27.4 Signature Compare Method238

4.28 Memory Test Summary240

4.29 Recommended Reading240

5 Embedded Core Test Fundamentals241

5.1.2 Introduction to Embedded Core-Based Chip Testing243

5.1.1 Purpose243

5.1 Introduction to Embedded Core Testing243

5.1.3 Reuse Cores244

5.1.4 Chip Assembly Using Reuse Cores244

5.2 What Is a Core?246

5.2.1 Defining Cores246

5.2.2 The Core DFT and Test Problem246

5.2.3 Built-In DFT246

5.3 What is Core-Based Design?248

5.3.1 Design of a Core-Based Chip248

5.3.2 Core-Based Design Fundamentals248

5.4.1 Embedded Core Deliverables250

5.4 Reuse Core Deliverables250

5.5 Core DFT Issues252

5.5.1 Embedded Core-Based Design Test Issues252

5.6 Development of a ReUsable Core256

5.6.1 Embedded Core Considerations for DFT256

5.7 DFT Interface Considerations—Test Signals262

5.7.1 Embedded Core Interface Considerations for DFT—Test Signals262

5.8 Core DFT Interface Concerns—Test Access265

5.8.1 Test Access to the Core Interface265

5.9.2 The Test Wrapper as a Frequency Interface268

5.9.1 The Test Wrapper as a Signal reduction Element268

5.9 DFT Interface Concerns—Test Wrappers268

5.9.3 The Test Wrapper as a Virtual Test Socket269

5.10 The Registered Isolation Test Wrapper271

5.11 The Slice Isolation Test Wrapper273

5.12 The Isolation Test Wrapper—Slice Cell275

5.13 The Isolation Test Wrapper—Core DFT Interface277

5.14 Core Test Mode Default Values279

5.14.1 Internal versus External Test Quiescence Defaults Application279

5.15.2 Test Clock Source Considerations281

5.15.1 Lack of Bidirectional Signals281

5.15 DFT Interface Wrapper Concerns281

5.16 DFT Interface Concerns—Test Frequency284

5.16.1 Embedded Core Interface Concerns for DFT—Test Frequency284

5.16.2 Solving the Frequency Problem284

5.17 Core DFT Development286

5.17.1 Internal Parallel Scan286

5.17.2 Wrapper Parallel Scan286

5.17.3 Embedded Memory BIST287

5.17.4 Other DFT Features287

5.18.1 Core DFT,Vectors,and Test Economics289

5.18.2 Core Selection with Consideration to DFT Economics289

5.18 Core Test Economics289

5.19 Chip Design with a Core292

5.19.1 Elements of a Core-Based Chip292

5.19.2 Embedded Core Integration Concerns292

5.19.3 Chip-Level DFT293

5.20 Scan Testing the Isolated Core296

5.21 Scan Testing the Non-Core Logic298

5.21.1 Scan Testing the Non-Core Logic in Isolation298

5.21.2 Chip-Level Testing and Tester Edge Sets298

5.22 User Defined Logic Chip-Level DFT Concerns300

5.23 Memory Testing with BIST302

5.24 Chip-Level DFT Integration Requirements304

5.24.1 Embedded Core-Based DFT Integration Architecture304

5.24.2 Physical Concerns305

5.25 Embedded Test Programs307

5.26 Selecting or Receiving a Core309

5.27 Embedded Core DFT Summary311

5.28 Recommended Reading311

About the CD313

Glossary of Terms317

Index341

About the Author348