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VLSI数字信号处理系统:设计与实现 英文版2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

VLSI数字信号处理系统:设计与实现 英文版
  • (美)帕赫著 著
  • 出版社: 北京:机械工业出版社
  • ISBN:7111123484
  • 出版时间:2003
  • 标注页数:784页
  • 文件大小:26MB
  • 文件页数:801页
  • 主题词:超大规模集成电路-数字信号-信号处理-英文

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图书目录

1 Introduction to Digital Signal Processing Systems1

1.1 Introduction1

1.2 Typical DSP Algorithms2

1.3 DSP Application Demands and Scaled CMOS Technologies27

1.4 Representations of DSP Algorithms31

1.5 Book Outline40

References41

2 Iteration Bound43

2.1 Introduction43

2.2 Data-Flow Graph Representations43

2.3 Loop Bound and Iteration Bound45

2.4 Algorithms for Computing Iteration Bound47

2.5 Iteration Bound of Multirate Data-Flow Graphs55

2.6 Conclusions57

2.7 Problems58

References61

3 Pipelining and Parallel Processing63

3.1 Introduction63

3.2 Pipelining of FIR Digital Filters64

3.3 Parallel Processing69

3.4 Pipelining and Parallel Processing for Low Power74

3.5 Conclusions82

3.6 Problems83

References88

4.1 Introduction91

4 Retiming91

4.2 Definitions and Properties93

4.3 Solving Systems of Inequalities95

4.4 Retiming Techniques97

4.5 Conclusions112

4.6 Problems112

References118

5 Unfolding119

5.1 Introduction119

5.2 An Algorithm for Unfolding121

5.3 Properties of Unfolding124

5.4 Critical Path, Unfolding, and Retiming127

5.5 Applications of Unfolding128

5.7 Problems140

5.6 Conclusions140

References147

6 Folding149

6.1 Introduction149

6.2 Folding Transformation151

6.3 Register Minimization Techniques157

6.4 Register Minimization in Folded Architectures163

6.5 Folding of Multirate Systems170

6.6 Conclusions174

6.7 Problems174

References186

7 Systolic Architecture Design189

7.1 Introduction189

7.2 Systolic Array Design Methodology190

7.3 FIR Systolic Arrays192

7.4 Selection of Scheduling Vector201

7.5 Matrix-Matrix Multiplication and 2D Systolic Array Design205

7.6 Systolic Design for Space Representations Containing Delays210

7.7 Conclusions213

7.8 Problems213

References223

8 Fast Convolution227

8.1 Introduction227

8.2 Cook-Toom Algorithm228

8.3 Winograd Algorithm237

8.4 Iterated Convolution244

8.5 Cyclic Convolution246

8.6 Design of Fast Convolution Algorithm by Inspection250

8.7 Conclusions251

8.8 Problems251

References253

9 Algorithmic Strength Reduction in Filters and Transforms255

9.1 Introduction255

9.2 Parallel FIR Filters256

9.3 Discrete Cosine Transform and Inverse DCT275

9.4 Parallel Architectures for Rank-Order Filters285

9.5 Conclusions297

9.6 Problems297

References310

10.1 Introduction313

10 Pipelined and Parallel Recursive and Adaptive Filters313

10.2 Pipeline Interleaving in Digital Filters314

10.3 Pipelining in 1st-Order IIR Digital Filters320

10.4 Pipelining in Higher-Order IIR Digital Filters325

10.5 Parallel Processing for IIR filters339

10.6 Combined Pipelining and Parallel Processing for IIR Filters345

10.7 Low-Power IIR Filter Design Using Pipelining and Parallel Processing348

10.8 Pipelined Adaptive Digital Filters351

10.9 Conclusions367

10.10 Problems367

References374

11 Scaling and Roundoff Noise377

11.1 Introduction377

11.2 Scaling and Roundoff Noise378

11.3 State Variable Description of Digital Filters382

11.4 Scaling and Roundoff Noise Computation386

11.5 Roundoff Noise in Pipelined IIR Filters391

11.6 Roundoff Noise Computation Using State Variable Description403

11.7 Slow-Down, Retiming, and Pipelining405

11.8 Conclusions410

11.9 Problems410

References419

12 Digital Lattice Filter Structures421

12.1 Introduction421

12.2 Schur Algorithm422

12.3 Digital Basic Lattice Filters429

12.4 Derivation of One-Multiplier Lattice Filter437

12.5 Derivation of Normalized Lattice Filter444

12.6 Derivation of Scaled-Normalized Lattice Filter447

12.7 Roundoff Noise Calculation in Lattice Filters454

12.8 Pipelining of Lattice IIR Digital Filters458

12.9 Design Examples of Pipelined Lattice Filters464

12.10 Low-Power CMOS Lattice IIR Filters469

12.11 Conclusions470

12.12 Problems470

References474

13 Bit-Level Arithmetic Architectures477

13.1 Introduction477

13.2 Parallel Multipliers478

13.3 Interleaved Floor-plan and Bit-Plane-Based Digital Filters489

13.4 Bit-Serial Multipliers490

13.5 Bit-Serial Filter Design and Implementation499

13.6 Canonic Signed Digit Arithmetic505

13.7 Distributed Arithmetic511

13.8 Conclusions518

13.9 Problems518

References527

14 Redundant Arithmetic529

14.1 Introduction529

14.2 Redundant Number Representations530

14.3 Carry-Free Radix-2 Addition and Subtraction531

14.4 Hybrid Radix-4 Addition536

14.5 Radix-2 Hybrid Redundant Multiplication Architectures540

14.6 Data Format Conversion545

14.7 Redundant to Nonredundant Converter547

14.8 Conclusions551

14.9 Problems552

References555

15 Numerical Strength Reduction559

15.1 Introduction559

15.2 Subexpression Elimination560

15.3 Multiple Constant Multiplication560

15.4 Subexpression Sharing in Digital Filters566

15.5 Additive and Multiplicative Number Splitting574

15.6 Conclusions583

15.7 Problems583

References589

16 Synchronous, Wave, and Asynchronous Pipelines591

16.1 Introduction591

16.2 Synchronous Pipelining and Clocking Styles593

16.3 Clock Skew and Clock Distribution in Bit-Level Pipelined VLSI Designs601

16.4 Wave Pipelining606

16.5 Constraint Space Diagram and Degree of Wave Pipelining612

16.6 Implementation of Wave-Pipelined Systems614

16.7 Asynchronous Pipelining619

16.8 Signal Transition Graphs622

16.9 Use of STG to Design Interconnection Circuits626

16.10 Implementation of Computational Units631

16.11 Conclusions640

16.12 Problems640

References643

17 Low-Power Design645

17.1 Introduction645

17.2 Theoretical Background648

17.3 Scaling Versus Power Consumption650

17.4 Power Analysis652

17.5 Power Reduction Techniques662

17.6 Power Estimation Approaches671

17.7 Conclusions688

17.8 Problems688

References692

18 Programmable Digital Signal Processors695

18.1 Introduction695

18.2 Evolution of Programmable Digital Signal Processors696

18.3 Important Features of DSP Processors697

18.4 DSP Processors for Mobile and Wireless Communications703

18.5 Processors for Multimedia Signal Processing704

18.6 Conclusions714

References714

Appendix A: Shortest Path Algorithms717

A.1 Introduction717

A.2 The Bellman-Ford Algorithm718

A.3 The Floyd-Warshall Algorithm720

A.4 Computational Complexities721

References722

Appendix B: Scheduling and Allocation Techniques723

B.1 Introduction723

B.2 Iterative/Constructive Scheduling Algorithms725

B.3 Transformational Scheduling Algorithms729

B.4 Integer Linear Programming Models738

References741

Appendix C: Euclidean GCD Algorithm743

C.1 Introduction743

C.2 Euclidean GCD Algorithm for Integers743

C.3 Euclidean GCD Algorithm for Polynomials745

Appendix D: Orthonormality of Schur Polynomials747

D.1 Orthogonality of Schur Polynomials747

D.2 Orthonormality of Schur Polynomials749

E.1 Introduction753

E.2 Multiplexer-Based Fast Binary Adders753

Appendix E: Fast Binary Adders and Multipliers753

E.3 Wallace Tree and Dadda Multiplier758

References761

Appendix F: Scheduling in Bit-Serial Systems763

F.1 Introduction763

F.2 Outline of the Scheduling Algorithm764

F.3 Minimum Cost Solution766

F.4 Scheduling of Edges with Delays768

References769

Appendix G: Coefficient Quantization in FIR Filters771

G.1 Introduction771

G.2 NUS Quantization Algorithm771

References774

Index775

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