面向集成电路电阻电容提取的高级场求解器技术 英文2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载

面向集成电路电阻电容提取的高级场求解器技术 英文PDF格式电子书版下载

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1 Introduction1

1.1 The Need for Parasitic Extraction1

1.2 The Methods for RC Extraction and Field Solver2

1.3 Book Outline4

1.4 Summary6

2 Basic Field-Solver Techniques for RC Extraction7

2.1 Problem Formulation7

2.2 Overview of the Numerical Methods10

2.3 Indirect Boundary Element Method11

2.4 Direct Boundary Element Method14

2.5 Floating Random Walk Method16

2.6 Summary18

3 Fast Boundary Element Methods for Capacitance Extraction(Ⅰ)19

3.1 Basics of Indirect Boundary Element Methods19

3.2 Fast Multipole Methods20

3.2.1 Introduction20

3.2.2 Multipole Expansions22

3.2.3 Local Expansions23

3.2.4 Fast Multipole Algorithm24

3.3 Low-Rank Matrix Compression-Based Fast Iterative Solvers26

3.3.1 Why Compression?26

3.3.2 Matrix Compression Can Reduce the Complexity to Linear27

3.3.3 Compression Possible?28

3.3.4 Basics of Matrix Compression Using SVD and QR30

3.3.5 Compression Without Building Entire Matrix Beforehand32

3.4 Matrix Compression by Adaptive Cross Approximation34

3.4.1 Adaptive Cross Approximation(ACA)35

3.4.2 Recompression of Adaptive Cross Approximation36

3.5 Summary37

4 Fast Boundary Element Methods for Capacitance Extraction(Ⅱ)39

4.1 Direct Boundary Element Method for Multi-dielectric Capacitance Extraction40

4.2 The Quasi-multiple Medium Approach43

4.2.1 Basic Idea43

4.2.2 Decomposition of Dielectrics and Boundary Element Partition45

4.2.3 Algorithm Description and Analysis47

4.3 Equation Organization and Solving Techniques49

4.3.1 Organization of the Coefficient Matrix49

4.3.2 Extended Jacobi and MN Preconditioners51

4.4 Numerical Results54

4.4.1 The Comparison with GIMEI54

4.4.2 The Comparison with ODDM55

4.4.3 The Results for Structures from Real Design57

4.4.4 The Comparison with FastCap59

4.5 Efficient Techniques for Handling Floating Metal Fills61

4.5.1 Basic Idea64

4.5.2 Equation Formation and Solution65

4.5.3 Numerical Results66

4.6 Summary70

5 Resistance Extraction of Complex 3-D Interconnects71

5.1 Analytical Resistance Formulation72

5.2 Field Solver for Interconnect Resistance72

5.2.1 Resistance Network of Multiterminal Regions73

5.2.2 Resistance Calculation Using Direct BEM74

5.3 Fast BEM Solver Using Linear Boundary Elements74

5.3.1 Physics-Based Nonuniform Virtual Cutting75

5.3.2 Discarding Conductors Not in the Path of Direct Current80

5.3.3 Dividing Elements Only in One Direction When Possible80

5.3.4 Linear Boundary Elements for Straight Conductors81

5.3.5 Efficiency Summary82

5.4 Analytical QBEM Extraction83

5.4.1 General Analytical QBEM Algorithm83

5.4.2 Distinguish Between Regular and Irregular Subregions84

5.4.3 Compute the Resistance Network of the Whole Region84

5.4.4 Numerical Result and Analysis85

5.5 Summary86

Appendix 5.A86

6 Substrate Resistance Extraction with Boundary Element Method91

6.1 Field Solver for Substrate Resistance92

6.2 Efficient Field-Solver Techniques95

6.2.1 Nonuniform Meshing95

6.2.2 Numerical Reduction of Linear Equation System96

6.2.3 Quasi-multiple Medium Technique to Sparsify Matrix99

6.3 Numerical Experiments100

6.3.1 Simple One-Layer Substrate100

6.3.2 The 52-Contact Structure with Three Doping Profiles102

6.3.3 Test Structure with Lateral Resistivity Variation104

6.4 Summary106

7 Extracting Frequency-Dependent Substrate Parasitics107

7.1 Field Solver for Substrate Capacitance and Resistance108

7.2 Direct Boundary Element Method for Substrate Impedance Extraction109

7.3 The Two-Step Approach110

7.3.1 Frequency-Dependent Entries in Matrix A111

7.3.2 Perturbed Equation System and Its Efficient Solution112

7.4 Efficient Technique for Solving the Real-Valued System114

7.5 Overall Algorithm Flow and Discussion115

7.6 Numerical Results116

7.6.1 Substrate with 52 Contacts116

7.6.2 More Numerical Experiments118

7.7 Summary119

8 Process Variation-Aware Capacitance Extraction121

8.1 Motivation121

8.2 The Incremental BEM for Variation-Aware Capacitance Library Building124

8.2.1 Basic Idea125

8.2.2 Modification of the Coefficient Matrix and the Solving Technique126

8.2.3 Numerical Results127

8.3 Preliminaries of Variation-Aware Statistical Capacitance Extraction128

8.3.1 Grid-Based Process Variation Model128

8.3.2 The Hermite Polynomial Collocation Method130

8.4 Chip-Level Statistical Capacitance Extraction Considering Spatial Correlation133

8.4.1 Intra-window Capacitance Extraction with the Grid-Based Variation Model134

8.4.2 Calculation of Inter-window Capacitance Covariance137

8.4.3 Complexity Analysis of the Inter-window Calculation139

8.4.4 Statistical Model of Full-Path Capacitance142

8.5 Experiments of Statistical Capacitance Extraction144

8.5.1 Simple Cases with Parallel-Line Structure145

8.5.2 A Large Case with Multilayered Structure147

8.6 Summary148

Appendix 8.A.Complete Proof of Theorem 8.3148

9 Statistical Capacitance Extraction Based on Continuous-Surface Geometric Model153

9.1 The Continuous-Surface Model for Geometric Variation154

9.1.1 Three Geometric Variation Models154

9.1.2 The Reasonable CSV Model for On-Chip Interconnect156

9.1.3 The Comparison of Three Geometric Variation Models158

9.2 Efficient Statistical Extraction Techniques161

9.2.1 The Weighted PFA for Variable Reduction162

9.2.2 Parallel Statistical Capacitance Extraction163

9.2.3 Calculating the Inter-window Covariance of Capacitance165

9.3 Fast Approaches to Model the Line-Edge Roughness167

9.3.1 Background167

9.3.2 The Adjoint Field Technique for Sensitivity Calculation169

9.3.3 Two Efficient Approaches170

9.3.4 Numerical Results173

9.3.5 More Analysis Results and Discussion176

9.4 Summary177

10 Fast Floating Random Walk Method for Capacitance Extraction179

10.1 The Basic Floating Random Walk Algorithms180

10.1.1 Numerical Technique to Calculate Multi-dielectric Surface Green's Function183

10.2 A Multi-dielectric FRW Algorithm with the Precharacterized Probabilities and Weight Values184

10.2.1 The Basic Idea184

10.2.2 The Details of the Precharacterization Procedure185

10.2.3 The FRW Algorithm with Multi-dielectric GFTs and WVTs189

10.3 The Techniques for Variance Reduction190

10.3.1 Background190

10.3.2 The Importance Sampling with the Weight Values Averaged192

10.3.3 The Comprehensive Variance Reduction Scheme195

10.4 The Space Management Technique and Parallel Implementation198

10.4.1 The Space Management Technique198

10.4.2 The Parallel Implementation200

10.5 Numerical Results201

10.5.1 Test Cases201

10.5.2 Validating the Multi-dielectric FRW Algorithm202

10.5.3 Validating the Variance Reduction Techniques205

10.5.4 Comparing with the Fast Boundary Element Method205

10.5.5 Validating the Efficiency of Parallel Computing207

10.6 Summary208

11 FRW-Based Solver for Chip-Scale Large Structures209

11.1 Motivation209

11.2 Basic Operations of Space Management and Accelerating Techniques210

11.2.1 Basic Operations211

11.2.2 Improving the Candidate Checking with Distance Limit212

11.2.3 Incomplete Candidate List215

11.2.4 Reducing the Time for Inquiring the Candidate List216

11.3 Space Management Structures and Approaches218

11.3.1 The Improved Octree-Based Approach219

11.3.2 Two Grid-Based Approaches220

11.3.3 The Hybrid Approach Using Grid and Octree221

11.4 Numerical Results223

11.4.1 Test Cases223

11.4.2 Validating the Three Accelerating Techniques224

11.4.3 Evaluating Different Space Management Approaches226

11.4.4 RWCap2 with the Hybrid Approach Using Grid and Octree229

11.4.5 The Results for Multi-dielectric Cases230

11.5 Summary231

References233

Index243